1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device which can improve an isolation characteristic and prevent a leakage current in conducting a borderless process, and a method for fabricating the same.
2. Background of the Related Art
A related art method for fabricating a semiconductor device will be explained with reference to the attached drawings. FIGS. 1A.about.1G illustrate sections showing the steps of a related art method for fabricating a semiconductor device.
Referring to FIG. 1A, the related art method for fabricating a semiconductor device starts with depositing an initial oxide film 2 and a nitride film 3 on a semiconductor substrate 1 having an active region and a field region defined thereon. As shown in FIG. 1B, the nitride film is subjected to selective patterning to expose the initial oxide film 2 in the field region.
Then the patterned nitride film 3 is used as a mask to etch the semiconductor substrate 1 to form trenches therein. The trenches may be formed by coating a photoresist film on an entire surface, patterning the photoresist film to expose the field region, and etching the semiconductor substrate 1. Then, a first oxide film 4 is deposited in the trenches by thermal oxidization. A buried insulating film is then deposited on an entire surface and etched by chemical mechanical polishing or etch back, to planarize the buried insulating film and the nitride film 3, thereby forming a trench isolation region 5 projected from an upper plane of the semiconductor substrate, as shown in FIG. 1C.
Then, as shown in FIG. 1D, the nitride film 3 and the initial oxide film 2 on the active region are removed.
As shown in FIG. 1E, a gate oxide film 6 is formed on the exposed active region, and a polysilicon layer 7 is deposited on an entire surface for forming a gate electrode. This can result in local recesses 13 at edges of a trench region caused by too much insulating film being removed by wet etching conducted before the gate oxide film is formed. This causes a gate-wraparound in which a recess portion at an edge in the active region is wrapped around by the gate electrode.
As shown in FIG. 1F, a mask for forming a gate is used in patterning the polysilicon layer 7 and the gate oxide film 6, to form a stack of a gate electrode 8 and a gate oxide film 6. The semiconductor substrate 1 on both sides of the gate electrode 8 is lightly doped with impurity ions. Then, an oxide film or a nitride film is deposited on an entire surface and etched back, to form sidewall spacers 9 at sides of the gate electrode 8 and the gate oxide film 6. Then the semiconductor substrate 1 on opposite sides of the sidewall spacers 9, excluding a portion under the gate electrode 8, is heavily with impurity ions, to form LDD source/drain regions 10.
Then, as shown in FIG. 1G, a planar protection film 11 is deposited on an entire surface. Then a contact hole is formed to each of the source/drain regions 10, and a contact plug 12 is formed in each of the contact holes. In FIG. 1G, if the contact holes are misaligned so that the trench isolation region 5 is reached in addition to reaching the source/drain region 10. Then the problem arises that the contact plug 12 will also make in contact with the semiconductor substrate 1 at an interface of the active region and the field region.
The aforementioned related art method for fabricating a semiconductor device has the following problems.
First, the thin gate oxide film, formed at recess portion 13, shortens a device lifetime because the gate oxide film is susceptible to loss.
Second, as a thickness of the gate oxide film in a recess region becomes thinner due to loss of an edge portion in a trench isolation region, the device becomes more likely to degrade due to an inverse narrow width effect in which a threshold voltage decreases as a width of the gate is reduced.
Third, a short between the contact plug and the semiconductor substrate occurs when the contact hole is misaligned to reach to the field region, which causes a leakage current.